1. Field of the Invention
The present invention relates generally to microelectronics layers susceptible to etching within fluorine containing plasmas followed by oxygen containing plasmas. More particularly, the present invention relates to methods for forming vias through microelectronics layers susceptible to etching within fluorine containing plasmas followed by oxygen containing plasmas.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and conductor element dimensions have decreased, it has become more common within the art of microelectronics fabrication to form interposed between the patterns of patterned microelectronics conductor layers low dielectric constant microelectronics dielectric layers. Low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically formed from carbon and/or hydrogen containing low dielectric constant dielectric materials such as but not limited to amorphous carbon dielectric materials, silsesquioxane spin-on-glass (SOG) dielectric materials and organic polymer spin-on-polymer dielectric materials. Particularly prevalent in the art of microelectronics fabrication are low dielectric constant dielectric layers formed from silsesquioxane spin-on-glass (SOG) dielectric materials.
Silsesquioxane spin-on-glass (SOG) dielectric materials are characterized by the general chemical formula R1-Si(OR2)3, where:(1) R1 may be any of several radicals, including but not limited to hydrogen radical and carbon bonded organic radicals, but not oxygen bonded radicals; and (2) R2 is typically, although not exclusively, a carbon bonded organic radical such as but not limited to methyl radical (--CH3) or ethyl radical (--C2H5). Low dielectric constant dielectric layers are typically formed from silsesquioxane spin-on-glass (SOG) dielectric materials through chemically and/or thermally induced condensation reactions which modify and cross-link the silicon-OR2 bonds of a silsesquioxane spin-on-glass (SOG) dielectric material, while typically leaving the silicon-R1 bond intact.
Low dielectric constant dielectric layers formed from low dielectric constant dielectric materials such as but not limited to amorphous carbon dielectric materials, silsesquioxane spin-on-glass (SOG) dielectric materials and organic polymer spin-on-polymer Dielectric materials are desirable interposed between the patterns of patterned microelectronics conductor layers within microelectronics fabrications since there is thus typically efficiently and manufacturably formed a microelectronics fabrication with an enhanced microelectronics fabrication speed, a decreased patterned microelectronics conductor layer parasitic capacitance and a decreased patterned microelectronics conductor layer cross-talk.
While low dielectric constant dielectric layers formed within microelectronics fabrications from low dielectric constant dielectric materials such as but not limited to amorphous carbon dielectric materials, silsesquioxane spin-on-glass (SOG) dielectric materials and organic polymer spin-on-polymer dielectric materials are thus desirable within the art of microelectronics fabrication, low dielectric constant dielectric layers are not formed entirely without problems within microelectronics fabrications.
In particular, it is known in the art of microelectronics fabrication that when attempting to form through a low dielectric constant dielectric layer formed from an amorphous carbon dielectric material or a silsesquioxane spin-on-glass (SOG) dielectric material a via while employing a conventional fluorine containing high density plasma (HDP) plasma etch method (ie: a plasma etch method having a plasma density of greater than about 1E11 per square centimeter) employing an etchant gas composition comprising a fluorine containing etchant gas, such as but not limited to a fluorocarbon etchant gas, there is typically observed a substantially attenuated etch rate of the low dielectric constant dielectric layer. In contrast, although enhanced etch rates of low dielectric constant dielectric layers formed from fluorine containing plasma etchable low dielectric constant dielectric materials such as but not limited to amorphous carbon dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials may be obtained when employing within microelectronics fabrications enhanced anisotropic etch methods, such as but not limited to magnetically enhanced reactive ion etch (MERLE) anisotropic etch methods, which also employ etchant gas compositions comprising fluorine containing etchant gases (such as fluorocarbon etchant gases), such enhanced anisotropic etch methods typically form upon the sidewall of a via formed through the low dielectric constant dielectric layer a fluorocarbon polymer residue layer. The fluorocarbon polymer residue layer when subsequently simultaneously stripped through a higher pressure (ie: reactor chamber pressure of from about 0.10 to about 10 torr) isotropic oxygen plasma etch method along with a patterned photoresist layer employed in defining the via typically laterally etches the low dielectric constant dielectric layer exposed within the via to form a laterally etched via. A series of schematic cross-sectional diagrams illustrating the results of progressive process stages in forming such a laterally etched via within such a low dielectric constant dielectric layer which in part defines the laterally etched via is shown within the schematic cross-sectional diagrams of FIG. 1 to FIG. 3.
Shown in FIG. 1 is a substrate 10 employed within a microelectronics fabrication, where the substrate 10 has formed thereupon a blanket low dielectric constant dielectric layer 12 which may be formed from a low dielectric constant dielectric material including but not limited to an amorphous carbon dielectric material or a silsesquioxane spin-on-glass (SOG) dielectric material. There is in turn formed upon the blanket low dielectric constant dielectric layer 12 a blanket silicon containing dielectric layer 14 which is typically formed of a silicon containing dielectric material such as but not limited to a silicon oxide dielectric material, a silicon nitride dielectric material or a silicon oxynitride dielectric material. Finally, there is formed upon the blanket silicon containing dielectric layer 14 a pair of patterned photoresist layers 16a and 16b.
Referring now to FIG. 2, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1. Shown in FIG. 2 is schematic cross-sectional diagram of a microelectronics fabrication otherwise equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein the blanket silicon containing dielectric layer 14 and the blanket low dielectric constant dielectric layer 12 have been sequentially patterned through use of a fluorine containing etching plasma 18, while employing the patterned photoresist layers 16a and 16b as an etch mask, to form: (1) the corresponding patterned silicon containing dielectric layers 14a and 14b; and (2) the corresponding patterned low dielectric constant dielectric layers 12a and 12b, which in the aggregate define a via 15 accessing the substrate 10. Upon the sidewalls of the via 15 there is formed a pair of fluorocarbon polymer residue layers 20a and 20b.
The fluorocarbon polymer residue layers 20a and 20b typically derive fluorine and carbon from a fluorocarbon etchant gas composition employed within the fluorine containing etching plasma 18, if a fluorocarbon etchant gas composition is employed, or in the alternative from fluorine within the fluorine containing etchant gas composition along with carbon which may be obtained from etching of a carbon containing blanket low dielectric constant dielectric layer 12 or through slight etching of the patterned photoresist layers 16a and 16b.
Referring now to FIG. 3, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2. Shown in FIG. 3 is a schematic cross-sectional diagram of a microelectronics fabrication in-part otherwise equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2, but wherein the patterned photoresist layers 16a and 16b, and the fluorocarbon polymer residue layers 20a and 20b, have been stripped from the microelectronics fabrication through use of an oxygen containing etching plasma 22 typically employing conventional oxygen containing plasma etching conditions including a reactor chamber pressure of from about 0.10 to about 10 torr. In the process of stripping from the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 2 the patterned photoresist layers 16a and 16b and the fluorocarbon polymer residue layers 20a and 20b to form the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 3, there is simultaneously typically also laterally (ie: isotropically) etched the patterned low dielectric constant dielectric layers 12a and 12b exposed within the via 15 sidewalls to form the laterally etched low dielectric constant dielectric layers 12a' and 12b' as illustrated in FIG. 3, which in conjunction with the patterned silicon containing dielectric layers 14a and 14b define a laterally etched via 15'.
Microelectronics fabrications analogous or equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 3 are undesirable within the art of microelectronics fabrication since it is often difficult to subsequently form void free microelectronics layers, such as but not limited to void free patterned microelectronics conductor stud layers, within undercut (ie: re-entrant) vias such as the laterally etched via 15'. It is thus towards the goal of forming within microelectronics fabrications while employing fluorine containing plasma etch methods vias through low dielectric constant dielectric layers formed of dielectric materials which are susceptible to sequential etching employing fluorine containing plasma etch methods followed by oxygen containing plasma etch methods, such dielectric materials including but not limited to amorphous carbon dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials, while avoiding laterally etching those vias when stripping from those microelectronics fabrications through oxygen containing plasma etch methods: (1) patterned photoresist layers employed in defining those vias; and (2)fluorocarbon polymer residue layers formed upon those via sidewalls incident to the fluorine containing plasma etch methods, that the present invention is more specifically directed.
In a more general sense, the present invention is also directed towards providing a method for forming a residue free via through a microelectronics layer formed from a material which is susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method, without laterally etching the via. Such materials include, but are not limited to, carbon materials (including but not limited to amorphous carbon materials, graphite materials and diamond materials), sulfur materials (including but not limited to amorphous sulfur materials and crystalline sulfur materials), silsesquioxane spin-on-glass (SOG) materials (as defined above) and incompletely cured silicate spin-on-glass (SOG) dielectric materials.
Various novel plasma etch methods and materials have been disclosed in the art of microelectronics fabrication.
For example, Wootton et al., in U.S. Pat. No. 5,496,438 discloses a method for removing from a patterned metal layer formed through a plasma etch method employing a corrosive plasma etchant gas composition a patterned photoresist etch mask layer employed in defining the patterned metal layer. Through the method there is etched the patterned photoresist etch mask layer in an oxygen gas plasma for a sufficiently long time and at a sufficiently high temperature (but beneath a melting temperature of the patterned metal layer) to remove all residual corrosive gas absorbed within the patterned photoresist layer, thus forming the patterned metal layer without staining.
In addition, Jones et al., in U.S. Pat. No. 5,632,855, discloses a plasma etch method for etching a thermal oxide layer within an integrated circuit microelectronics fabrication. The method employs various plasma etchant gas compositions comprising various concentrations of argon, carbon tetrafluoride and trifluoromethane employed within various sequential process steps including etch pre-stabilizing process steps, etch process steps, etch post-stabilizing process steps and particle flush process steps, to provide a plasma etched thermal oxide layer of enhanced thickness uniformity across a semiconductor substrate, including contact regions of the semiconductor substrate.
Finally, Chang, in U.S. Pat. No. 5,643,407, discloses a method for forming vias through sandwich composite spin-on-glass (SOG) dielectric layers within integrated circuit microelectronic fabrications. The method employs a nitrogen plasma treatment of exposed portions of the spin-on-glass (SOG) dielectric layers within the vias to provide vias with attenuated susceptibility to moisture absorption and outgassing which corrodes patterned conductor metal layers subsequently formed within those vias.
Desirable in the art of microelectronics fabrication are methods through which there may be formed residue free vias through microelectronics layers formed of materials susceptible to sequential etching employing fluorine containing plasma etch methods followed by oxygen containing plasma etch methods, without laterally etching the vias. More particularly desirable in the art of microelectronics fabrication are fluorine containing plasma etch methods through which there may be formed residue free vias through low dielectric constant dielectric layers formed of low dielectric constant dielectric materials which are susceptible to sequential etching employing fluorine containing plasma etch methods followed by oxygen containing plasma etch methods, such materials including but not limited to amorphous carbon dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials, without laterally etching the vias when stripping from the microelectronics fabrications through the oxygen containing plasma etch methods patterned photoresist layers employed in defining the vias and fluorocarbon polymer residue layers which are formed upon the via sidewalls incident to the fluorine containing plasma etch methods. It is towards these goals that the present invention is both generally and more specifically directed.